1. Field of the Invention
The invention relates to a thin film capacitor used as an element in various electronic circuits, and also to a wiring-patterned structure used in a wiring board.
2. Description of the Related Art
There has been know a single-layered thin film capacitor including a first electrode layer, a dielectric layer formed on the first electrode layer, and a second electrode layer formed on the dielectric layer, as suggested in Japanese Unexamined Patent Publication Nos. 5-226844, 8-88318 and 10-154878. There has been also known a thin film capacitor having a multi-layered substrate including a substrate, a ground layer formed on the substrate, a dielectric layer formed on the ground layer, and an electrically conductive layer formed on the dielectric layer, as suggested in Japanese Unexamined Patent Publication Nos. 7-30257 and 7-307567.
These thin film capacitors are generally designed to include an upper electrode, a lower electrode, and a dielectric layer sandwiched between the upper and lower electrodes, and are accompanied with the following problems.
The first problem is that the upper electrode is liable to short-circuit with the lower electrode.
FIG. 1A is a cross-sectional view of a thin film capacitor. The illustrated thin film capacitor is comprised of a substrate 90, a lower electrode 91 formed on the substrate 90, a dielectric layer 92 formed on the lower electrode 91, and an upper electrode 93 formed on the dielectric layer 92.
If the thin film capacitor is properly fabricated in such a configuration as designed, the thin film capacitor would have such a structure as illustrated in FIG. 1A. However, if the upper electrode 93 is formed out of place, for instance, the upper electrode 93 would make contact with the lower electrode 91, resulting in occurrence of short-circuit between the upper electrode 93 and the lower electrode 91, as illustrated in FIG. 1B.
The upper electrode 93 may be designed to have a width smaller than a width of the lower electrode 91 in order to avoid such short-circuit, which, however, would cause a problem that a capacitor has to be formed in a greater size for ensuring a desired capacity. This results in reduction in a density of wiring. In order to avoid reduction in a capacity of a capacitor, it would be necessary to re-design a capacitor with respect to configuration thereof.
The second problem is that it is difficult to form multi-layered wirings in the above-mentioned capacitor having a multi-layered structure. A multilayered wiring substrate including a thin film capacitor therein is formed with via-holes in order to electrically connect electrodes of thin film capacitors formed in upper and lower layers, to each other.
As such a via-hole, there are known a filled via-hole as shown in Japanese Unexamined Patent Publication No. 7-30257 and a postless via-hole as shown in Japanese Unexamined Patent Publication No. 7-307567. A filled via-hole is used more widely than a postless via-hole. This is because that a filled via-hole can vertically connect an electrode formed in an upper layer to an electrode layer formed in a lower layer to thereby increase a wiring density.
However, when a filled via-hole is formed in the above-mentioned capacitor having a multi-layered structure, it is unavoidable that there is formed a step having a height in the range of 2 to 20 .mu.m between the upper and lower electrodes. As a result, there is also formed a step or irregularity on an outer surface of a resultant thin film capacitor. Thus, it is quite difficult to properly form a power-feeding layer absolutely required for formation of a filled via-hole.
FIG. 2 illustrates a thin film capacitor in which this problem is caused. The illustrated thin film capacitor is comprised of a substrate 94, a lower electrode 95, a dielectric layer 96 formed on the lower electrode 95, an upper electrode 97 formed on the dielectric layer 96, and a power-feeding layer 98 covering the upper electrode 97, the dielectric layer 96 and the lower electrode 95 therewith. A filled via-hole 99 is formed above the upper electrode 97.
As illustrated in FIG. 2, the lower electrode 95 is liable to be reverse-tapered when patterned. As a result, there is formed a step between the substrate 94 and the lower electrode 95, which would cause breakage of the power-feeding layer 98. Thus, a filled via-hole is liable to be improperly formed.
Though Japanese Unexamined Patent Publication No. 10-154878 has suggested a solution to this problem, the suggested solution is accompanied with another problem that fabrication steps become unavoidably complicated.
The third problem is that the above-mentioned capacitor having a multi-layered structure is fabricated through a quite complicated fabrication process. This is because it is necessary in the process to carry out film deposition and film patterning for each of electrode layers and a dielectric layer.
The fourth problem is that a dielectric layer is sometimes deteriorated in quality during a thin film capacitor fabrication process.
A dielectric layer is patterned generally through a dry etching step and a washing step for removal of etching residue. Removal of etching residue has to be absolutely carried out for enhancement in reliability of a thin film capacitor. In general, acid is selected for washing in order to sufficiently wash a dielectric layer. However, since etching residue is composed mainly of a material resulted from reaction between a dielectric material of which a dielectric layer is composed and etching gas, acid which is capable of dissolving etching residue can dissolve the dielectric layer. As a result, the dielectric layer is partially reduced in a thickness or is subject to alteration in composition.
This problem as mentioned above occurs when a dielectric layer is patterned by wet etching through the use of acid, as well as when a dielectric layer is patterned by dry etching. Furthermore, the above-mentioned problem remarkable occurs when a dielectric layer is composed of perovskite-structured material such as BST (Ba.sub.X Sr.sub.1-X TiO.sub.3), PZT (PbZr.sub.X Ti.sub.1-X O.sub.3), PLZT (Pb.sub.1-Y La.sub.Y Zr.sub.X Ti.sub.1-X O.sub.3) and SrBi.sub.2 Ta.sub.2 O.sub.9. Such perovskite-structured material is preferably used to a need for fabricating a capacitor in a smaller size with a higher capacity. However, if such perovskite-structured materials washed with acid, particular ingredients are dissolved out, which would cause alteration in composition. The materials having perovskite-structure have electricity characteristic which significantly varies due to even small alteration in composition, resulting in that the above-mentioned problem becomes remarkable.
On the other hand, conventional methods of forming an electrically conductive wiring can be grouped into a subtractive method and an additive method. A subtractive method is a method in which an electrically conductive wiring is formed by etching a copper foil formed on a substrate or a resin. For instance, Japanese Unexamined Patent Publication No. 10-51105 has suggested one of such subtractive methods. An additive method is a method in which an electrically conductive wiring is formed by electroless plating or electroplating.
The above-mentioned additive method may be grouped further into a semi-additive method as suggested in Japanese Unexamined Patent Publication No. 9-64493 and a full additive method as suggested in Japanese Unexamined Patent Publication No. 6-334334. A semi-additive method is a method in which an electrical conductor is formed in a resist film by electroplating after formation of a power-feeding layer, and, after removal of the resist film, the power-feeding layer is etched into a wiring pattern. A full additive method is a method in which a resist film is patterned after a substrate has been activated at a surface thereof, and an electrical conductor is formed by electroless plating with the resist film being used as a mask.
The above-mentioned subtractive and semi-additive methods are both accompanied with a problem that since a via-hole, which is a vertically extending passage for electrically connecting upper and lower wiring layers to each other, is reverse-tapered in shape, high reliability in electrical connection cannot be ensured.
In addition, such reverse-shaped via-hole provides only small designability, because another via-hole cannot be formed above the previously formed via-hole.
Furthermore, since a patterned electrical conductor projects above a substrate and an insulating resin layer, when there is to be formed a multi-layered wiring structure by forming an insulating layer and then another patterned electrical conductor above the previously formed electrical conductor, it would be quite difficult to reduce the insulating layer in thickness, and remove irregularity at a surface to thereby planarize the multi-layered wiring structure.
The full additive method in which an electrical conductor is formed by electroless plating has an advantage that it is possible to form the electrical conductor without steps, or planarize the electrical conductor, because it is relatively easy to equalize a thickness of a patterned resist film to a thickness of an electrical conductor.
However, since a patterned resist film is formed after catalyser has been absorbed into a substrate or an insulating resin film, there are caused problems that metal is not precipitated in plating because catalyser has been removed in a step of developing the resist film, which causes breakage of a wiring, and that adhesion between the resist film and an underlying layer is weakened.
In addition, since catalyser remains in a region where a patterned electrical conductor is not formed, migration of metal ions is liable to occur, which reduces reliability in electrical insulation. This problem becomes more remarkable in fabrication of a wiring in a smaller size.
Japanese Unexamined Patent Publication No. 63-305550 has suggested a semiconductor memory device including a memory cell comprised of a capacitor and a transistor. A semiconductor substrate is formed with a trench. A capacitor dielectric film is formed on an inner wall of the trench. A capacitor electrode is completely buried in the trench without extending to a surface of the semiconductor substrate. The capacitor dielectric film has a cutout portion through which the capacitor electrode makes electrical contact with a source or drain of the transistor.
Japanese Unexamined Patent Publication No. 2-303091 has suggested a substrate including a capacitor formed therein, wherein a portion of the substrate acts as a dielectric layer of the capacitor. First and second terminal electrodes are formed on an upper surface of the substrate in electrical isolation to each other, and electrode patterns are formed on a lower surface of the substrate in symmetrical location of the first and second terminal electrodes about the substrate. A first capacitor is formed between the first terminal electrode and one of the electrode patterns, and a second capacitor is formed between the second terminal electrode and the other of the electrode patterns. The first and second capacitors cooperate to each other to form a series circuit, which constitutes the capacitor formed in the substrate.
Japanese Unexamined Patent Publication No. 10-56148 has suggested a ferroelectric memory device including an insulating substrate, a semiconductor layer formed on a surface of the insulating substrate, a field effect transistor formed in the semiconductor layer, a column-shaped lower electrode making electrical contact with a diffusion layer of the field effect transistor and buried in the insulating substrate, a ferroelectric film at least partially covering a periphery of the lower electrode therewith, and an upper electrode covering the ferroelectric film therewith.
Japanese Unexamined Patent Publication No. 6-140733 has suggested a circuit board including an insulator having input and output terminals and a wiring layer at a surface thereof, input and output pads formed on the input and output terminals, and a mount formed on the wiring layer for mounting a semiconductor device with a solder bump sandwiched therebetween. The input and output pads include first nickel-plated layers formed on the input and output terminals, and a second nickel-plated layer formed on the first nickel-plated layers by electroless plating. The mount includes a nickel-sputtered layer formed on the wiring layer by sputtering, and a third nickel-plated layer formed on the nickel-sputtered layer by electroless plating.
Japanese Unexamined Patent Publication No. 8-97214 has suggested a method of fabricating a semiconductor device, including the steps of forming an opening in an insulating film formed on a semiconductor substrate, to thereby expose an underlying semiconductor region, forming an adhesive barrier metal layer by depositing an adhesive metal film having high adhesion with the insulating film, and a barrier metal film, depositing a first metal film, oxide of which is an insulator, to thereby cover a surface of the insulating film, a sidewall of the opening and an exposed surface of the semiconductor region, burying a mask in the opening, oxidizing the first metal film though the use of the mask, removing the mask, filling the opening with metal by plating, removing the oxide and a portion of the first metal film located just below the oxide to thereby expose the barrier metal film, and forming a second metal film as an upper wiring in selected regions.
Japanese Unexamined Patent Publication No. 6-132661 has suggested a method of fabricating a multi-layered wiring structure including first and second insulating layers each composed of photosensitive resin and first and second circuit patterns each composed of metal, said insulating layers and said circuit patterns being alternately deposited one on another, the method comprising the steps of forming a two-layered pre-circuit pattern on the first insulating layer by etching or lift-off, said pre-circuit pattern including a first layer for preventing diffusion, composed of metal having high adhesion to the first insulating layer, and a second layer for preventing oxidation, composed of metal which has high resistance to oxidation, forming a third layer on the pre-circuit pattern by plating, said third layer being composed of highly electrically conductive metal, forming a fourth layer on the third layer by plating, said fourth layer being composed of metal which does not react with photosensitive resin, forming the second insulating layer on the second circuit pattern, and repeating the above-mentioned steps.
Japanese Unexamined Patent Publication No. 8-83796 has suggested electroless plating bath used for forming a wiring layer in a semiconductor device, comprising metal containing metal ions, a reducing agent containing no metals in a chemical formula thereof and reducing said metal ions, a complexing agent containing no metals in a chemical formula thereof and complexing said metal ions, and a pH adjuster containing no metals in a chemical formula thereof